1. Field of the Invention
This invention generally relates to a method for manufacturing a capacitor of semiconductor memory device, more particularly to a method for manufacturing a capacitor of semiconductor memory device capable of increasing surface area of a storage node electrode of a capacitor.
2. Description of the Related Art
As the integrity of memory device increases, cell dimension and gap between cells decrease. However, currently it is still required a capacitor having large capacitance and also occupying smaller dimension since the capacitor should hold a regular degree of capacitance.
Conventionally, a cylinder type storage electrode occupying smaller dimension and large capacitance has been widely used.
FIGS. 3A to 3D illustrate manufacturing process of a conventional cylinder type capacitor.
Referring to FIG. 3A, a planarization layer 302 is formed on a semiconductor substrate 300 in which a transistor(not shown) and a storage node 301 are formed. An oxide layer of intermetal insulating layer 304 is formed on the planarization layer 302. The intermetal insulating layer 304 and the planarization layer 302 are etched to expose a storage node 301 so that a storage node contact hole H is formed.
Referring to FIG. 3B, a first polysilicon layer 306 for storage node electrode is formed on the intermetal insulating layer 304 to be contacted with the exposed storage node 301. A sacrifice oxide layer 308 has a planarization property and is made of a layer having excellent wet-etching selectivity ratio to the polysilicon layer, such as a PSG layer. the sacrifice oxide layer 308 and the first polysilicon layer 306 are patterned by selected portions thereof such that they are remained within the storage node contact hole H.
Referring to FIG. 3C, a second polysilicon layer for storage node electrode is formed on the intermetal insulating layer 304 and on the sacrifice layer 308. Then this, the second polysilicon layer is blanket-etched to expose those surfaces of the sacrifice oxide layer 108 and the second intermetal layer 304 thereby forming a polysilicon-spacer 310 at a sidewall of the sacrifice oxide layer 308. Consequently, a storage node electrode 312 comprising the first polysilicon layer 306 and the polysilicon-spacer 310 is formed.
As shown in FIG. 3D, the sacrifice oxide layer 308 is removed by the wet-etching process. Afterward, a dielectric layer 314 is coated on the surface of storage node electrode 312 and on the second intermetal insulating layer 304. As for the dielectric layer 314, for example, an Oxide-Nitride-Oxide(ONO) and a Nitride-Oxide(NO) can be used. Next, a plate electrode 316 is formed on the surface of the dielectric layer 314 thereby accomplishing the cylinder type capacitor.
However, the above cylinder type capacitor is increased as much as the height of spacer. At this time, the step difference of a cell region in which a capacitor is formed and a peripheral region is increased when the height of spacer is increased so as to increase the capacitance. As a result, it is very difficult to align a mask for forming a photoresist pattern precisely and it is also difficult to obtain sufficient process margin during a subsequent photolithography process.
Accordingly, in view of the occurrence of step difference in the cell region and the peripheral region, the cylinder type capacitor has a limitation of the increase in the capacitance. Therefore, the conventional cylinder type capacitor is not suitable for the semiconductor device which requires high integrity.